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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt
Rev. 03 -- 9 November 2009 Product data sheet
1. General description
The PCA9575 is a CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion in low voltage processor and handheld battery powered mobile applications and was developed to enhance the NXP family of I2C-bus I/O expanders. The improvements include lower supply current, lower operating voltage of 1.1 V to 3.6 V, separate supply rails to allow voltage level translation anywhere between 1.1 V and 3.6 V, 400 kHz clock frequency, and smaller packaging. Any of the 16 I/O ports can be configured as an input or output independent of each other and default on start-up to inputs. I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum; for example in battery powered mobile applications and clamshell devices for interfacing to sensors, push buttons, keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage level to I/O devices operating at a different (usually higher) voltage level. PCA9575 has built-in level shifting feature that makes these devices extremely flexible in mixed signal environments where communication between incompatible I/Os is required. The core of PCA9575 can operate at a voltage as low as 1.1 V while each I/O bank can operate in the range 1.1 V to 3.6 V. Bus hold with programmable on-chip pull-up or pull-down feature for I/Os is also provided. The output stage consists of two banks each of 8-bit configuration registers, input registers, interrupt mask registers, output registers, bus-hold and pull-up/pull-down registers and polarity inversion registers. These registers allow the system master to program and configure 16 GPIOs through the I2C-bus. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the read registers can be inverted with the Polarity Inversion register (active HIGH or active LOW operation). Either a bus-hold function or pull-up/pull-down feature can be selected by programming corresponding registers. The bus-hold provides a valid logic level when the I/O bus is not actively driven. When bus-hold feature is not selected, the I/O ports can be configured to have pull-up or pull-down by programming the pull-up/pull-down configuration register. An open-drain interrupt output pin (INT) allows monitoring of the input pins and is asserted each time a change occurs on an input port unless that port is masked (default = masked). A `GPIO All Call' command allows programming multiple PCA9575s at the same time even if they have different individual I2C-bus addresses. This allows optimal code programming when more than one device needs to be programmed with the same instruction or if all outputs need to be turned on or off at the same time. The internal
NXP Semiconductors
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
Power-On Reset (POR) or hardware reset pin (RESET) initializes the two banks of 8 I/Os as inputs, sets the registers to their default values and initializes the device state machine. The I/O banks are held in its default state when the logic supply (VDD) is off. The PCA9575 is available in 24-pin TSSOP, 28-pin TSSOP and HWQFN24 packages, and is specified over the -40 C to +85 C industrial temperature range. The 28-pin package provides four address select pins, allowing up to 16 PCA9575 devices to be connected with 16 different addresses on the same I2C-bus.
2. Features
I Separate supply rails for core logic and each of the two I/O banks provides voltage level shifting I 1.1 V to 3.6 V operation with level shifting feature I Very low standby current: < 2 A I 16 configurable I/O pins organized as 2 banks that default to inputs at power-up I Outputs: N Totem pole: 1 mA source and 3 mA sink N Independently programmable 100 k pull-up or pull-down for each I/O pin N Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level change of pins programmed as inputs I Inputs: N Programmable bus hold provides valid logic level when inputs are not actively driven N Programmable Interrupt Mask Control for input pins that do not require an interrupt when their states change or to prevent spurious interrupts default to mask at power-up N Polarity Inversion register allows inversion of the polarity of the I/O pins when read I 400 kHz I2C-bus serial interface I Compliant with I2C-bus Standard-mode (100 kHz) I Active LOW reset (RESET) input pin resets device to power-up default state I GPIO All Call address allows programming of more than one device at the same time with the same parameters I 16 programmable slave addresses using 4 address pins (28-pin TSSOP only) I -40 C to +85 C operation I ESD protection exceeds 6000 V HBM per JESD22-A114, 500 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Packages offered: TSSOP28, TSSOP24, HWQFN24
PCA9575_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 9 November 2009
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NXP Semiconductors
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
3. Applications
I I I I I I I I I I I I Cell phones Media players Multi-voltage environments Battery operated mobile gadgets Motherboards Servers RAID systems Industrial control Medical equipment PLCs Gaming machines Instrumentation and test measurement
4. Ordering information
Table 1. Ordering information Topside mark PCA9575PW2 PA9575PW1 575F Package Name PCA9575PW2 PCA9575PW1 PCA9575HF TSSOP28 TSSOP24 HWQFN24 Description plastic thin shrink small outline package; 28 leads; body width 4.4 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.75 mm Version SOT361-1 SOT355-1 SOT994-1 Type number
PCA9575_3
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Product data sheet
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
5. Block diagram
PCA9575
A0
(1)
VDD(IO)1 P1_0 P1_1 8-bit INPUT/ OUTPUT PORTS BANK 1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7 I2C-BUS/SMBus CONTROL P0_0 VDD(IO)0
A1 A2 A3
write pulse read pulse
SCL SDA
INPUT FILTER
P0_1 8-bit INPUT/ OUTPUT PORTS BANK 0 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7 VDD
write pulse VDD RESET POWER-ON RESET read pulse
VSS LP FILTER
002aad562
INT
Remark: All I/Os are set to inputs at power-up and RESET. (1) PCA9575PW2 only.
Fig 1.
Block diagram of PCA9575
PCA9575_3
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Product data sheet
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
data from shift register
configuration register D FF Q
Q1
output port register data VDD(IO)
data from shift register write configuration pulse write pulse
CK
Q
D FF CK
Q P0_0 to P0_7 P1_0 to P1_7
Q2
output port register
input port register D FF Q
ESD protection diode
VSS input port register data INTERRUPT MASK
read pulse VDD(IO) BUS-HOLD AND PULL-UP/PULL-DOWN CONTROL
CK
to INT
100 k
polarity inversion register data from shift register write polarity pulse D FF CK
002aad566
Q
polarity inversion register data
Fig 2.
Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)
PCA9575_3
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Product data sheet
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NXP Semiconductors
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
6. Pinning information
6.1 Pinning
A0 VDD VDD RESET P0_0 P0_1 P0_2 P0_3 VDD(IO)0 P0_4 P0_5 1 2 3 4 5 6 7 8 9 24 SCL 23 SDA 22 P1_0 21 P1_1 20 P1_2 19 P1_3 18 VDD(IO)1 17 P1_4 16 P1_5 15 P1_6 14 P1_7 13 VSS
002aad564
1 2 3 4 5 6 7 8 9
28 SCL 27 SDA 26 P1_0 25 P1_1 24 P1_2 23 P1_3 22 A3 21 VDD(IO)1 20 P1_4 19 P1_5 18 P1_6 17 P1_7 16 VSS 15 A2
002aad563
RESET P0_0 P0_1 P0_2 P0_3 A1 VDD(IO)0
PCA9575PW2
PCA9575PW1
P0_4 10 P0_5 11 P0_6 12 P0_7 13 INT 14
P0_6 10 P0_7 11 INT 12
Fig 3.
Pin configuration for TSSOP24
23 RESET
Fig 4.
Pin configuration for TSSOP28
24 P0_0
terminal 1 index area P0_1 P0_2 P0_3 VDD(IO)0 P0_4 P0_5 1 2 3 4 5 6
19 P1_0 18 P1_1 17 P1_2 16 P1_3 15 VDD(IO)1 14 P1_4 13 P1_5 P1_6 12
002aad575
PCA9575HF
VSS 10
Transparent top view
Fig 5.
Pin configuration for HWQFN24
PCA9575_3
P1_7 11
7
8
P0_6
P0_7
INT
9
20 SDA
21 SCL
22 VDD
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
6.2 Pin description
Table 2. Symbol A0 VDD RESET P0_0 P0_1 P0_2 P0_3 A1 VDD(IO)0 P0_4 P0_5 P0_6 P0_7 INT A2 VSS P1_7 P1_6 P1_5 P1_4 VDD(IO)1 A3 P1_3 P1_2 P1_1 P1_0 SDA SCL
[1]
Pin description Pin TSSOP28 TSSOP24 HWQFN24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 22 23 24 1 2 3 4 5 6 7 8 9 10[1] 11 12 13 14 15 16 17 18 19 20 21 I power supply I I/O I/O I/O I/O I power supply I/O I/O I/O I/O O I ground I/O I/O I/O I/O power supply I I/O I/O I/O I/O I/O I address input 0 supply voltage active LOW reset input port 0 input/output 0 port 0 input/output 1 port 0 input/output 2 port 0 input/output 3 address input 1 I/O supply voltage for bank 0 port 0 input/output 0 port 0 input/output 1 port 0 input/output 2 port 0 input/output 3 interrupt output (open-drain; active LOW) address input 2 supply ground port 1 input/output 4 port 1 input/output 5 port 1 input/output 6 port 1 input/output 7 I/O supply voltage for bank 1 address input 3 port 1 input/output 3 port 1 input/output 2 port 1 input/output 1 port 1 input/output 0 serial data line serial clock line Type Description
HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.
PCA9575_3
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Product data sheet
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
7. Functional description
7.1 I/O ports
The 16 I/O ports are organized as two banks of 8 ports each. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion register. Either a bus-hold function or pull-up/pull-down feature can be selected by programming corresponding registers. A bus-hold provides a valid logic level when the I/O bus is not actively driven. It consists of a pair of buffers, one being weak (low drive-strength), that latch the input at the last driven value. This prevents the input from floating while it is being driven by a 3-state output. Latching the last valid logic state of input prevents it from settling at a midpoint between VDD and ground that in turn consumes power. An active bus driver can easily override the logic level set by the bus-keeper. When bus-hold feature is not selected, the I/O ports can be configured to have pull-up or pull-down by programming the pull-up/pull-down configuration register.
7.2 Device address
Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). Address configuration for the device depends on the package type chosen. The device offered in a 24-pin package will have a fixed slave address for the PCA9575 as shown in Figure 6.
slave address 0 1 0 0 fixed 0 0 0 R/W
002aad567
Fig 6.
PCA9575 device address for 24-pin version
The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while logic 0 selects a write operation. The slave address for the 28-pin version of the PCA9575 is shown in Figure 7.
slave address 0 1 fixed 0 A3 A2 A1 A0 R/W
hardware selectable
002aad583
Fig 7.
PCA9575 device address for 28-pin version
PCA9575_3
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Product data sheet
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
7.3 Command register
Following the successful acknowledgement of the slave address + R/W bit, the bus master will send a byte to the PCA9575, which will be stored in the Command register.
AI
0
0
0
D3
D2
D1
D0
Auto-Increment flag
register address
002aad568
Reset state = 00h Remark: The Command register does not apply to Software Reset I2C-bus address.
Fig 8.
Command register
The lowest 4 bits are used as a pointer to determine which register will be accessed. Only a Command register code with the 4 least significant bits equal to the 16 allowable values as defined in Table 3 "Register summary" will be acknowledged. Reserved or undefined command codes will not be acknowledged. At power-up, this register defaults to 00h, with the AI bit set to logic 0, and the lowest 4 bits set to logic 0. If the Auto-Increment flag is set (AI = 1), the 4 least significant bits of the Command register are automatically incremented after a read or write. This allows the user to program and/or read the 16 command registers (listed in Table 3) sequentially. It will then roll over to register 00h after the last register is accessed and the selected registers will be overwritten or re-read. If the Auto-Increment flag is cleared (AI = 0), the 4 least significant bits are not incremented after data is read or written, only one register will be repeatedly read or written.
7.4 Register definitions
Table 3. 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch Register summary D3 0 0 0 0 0 0 0 0 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 Name IN0 IN1 INVRT0 INVRT1 BKEN0 BKEN1 PUPD0 PUPD1 CFG0 CFG1 OUT0 OUT1 MSK0 Type read only read only read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write Function Input port 0 register Input port 1 register Polarity inversion port 0 register Polarity inversion port 1 register Bus-hold enable 0 register Bus-hold enable 1 register Pull-up/pull-down selector port 0 register Pull-up/pull-down selector port 1 register Configuration port 0 register Configuration port 1 register Output port 0 register Output port 1 register Interrupt mask port 0 register Register number
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Product data sheet
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
Table 3. 0Dh 0Eh 0Fh
Register summary ...continued D3 1 1 1 D2 1 1 1 D1 0 1 1 D0 1 0 1 Name MSK1 INTS0 INTS1 Type read/write read only read only Function Interrupt mask port 1 register Interrupt status port 0 register Interrupt status port 1 register
Register number
7.5 Writing to port registers
Data is transmitted to the PCA9575 by sending the device address and setting the least significant bit to logic 0 (see Figure 6 or Figure 7 for device address). The command byte is sent after the address and determines which register will receive the data following the command byte. Each 8-bit register may be updated independently of the other registers.
7.6 Reading the port registers
In order to read data from the PCA9575, the bus master must first send the PCA9575 address with the least significant bit set to a logic 0 (see Figure 6 or Figure 7 for device address). The command byte is sent after the address and determines which register will be accessed. After a restart, the device address is sent again but this time, the least significant bit is set to logic 1. Data from the register defined by the command byte will then be sent by the PCA9575. Data is clocked into the register on the falling edge of the acknowledge clock pulse. After the first byte is read, additional bytes may be read using the auto-increment feature.
7.6.1 Register 0 - Input port 0 register
This register is read-only. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. Writes to this register will be acknowledged but will have no effect. The default `X' is determined by the externally applied logic level.
Table 4. Bit 7 6 5 4 3 2 1 0 Register 0 - Input port 0 register (address 00h) bit description Symbol IO0.7 IO0.6 IO0.5 IO0.4 IO0.3 IO0.2 IO0.1 IO0.0 Access read only read only read only read only read only read only read only read only Value X X X X X X X X Description determined by externally applied logic level
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
7.6.2 Register 1 - Input port 1 register
This register is read-only. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. Writes to this register will be acknowledged but will have no effect. The default `X' is determined by the externally applied logic level.
Table 5. Bit 7 6 5 4 3 2 1 0 Register 1 - Input port 1 register (address 01h) bit description Symbol IO1.7 IO1.6 IO1.5 IO1.4 IO1.3 IO1.2 IO1.1 IO1.0 Access read only read only read only read only read only read only read only read only Value X X X X X X X X Description determined by externally applied logic level
7.6.3 Register 2 - Polarity inversion port 0 register
This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with `1'), the corresponding Input port data is inverted. If a bit in this register is cleared (written with a `0'), the Input port data polarity is retained.
Table 6. Register 2 - Polarity Inversion port 0 register (address 02h) bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 0* 0* 0* 0* 0* 0* 0* 0* Description inverts polarity of Input port 0 register data 0 = Input port 0 register data retained (default value) 1 = Input port 0 register data inverted
PCA9575_3
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
7.6.4 Register 3 - Polarity inversion port 1 register
This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with `1'), the corresponding Input port data is inverted. If a bit in this register is cleared (written with a `0'), the Input port data polarity is retained.
Table 7. Register 3 - Polarity Inversion port 1 register (address 03h) bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 0* 0* 0* 0* 0* 0* 0* 0* Description inverts polarity of Input port 1 register data 0 = Input port 1 register data retained (default value) 1 = Input port 1 register data inverted
7.6.5 Register 4 - Bus-hold/pull-up/pull-down enable 0 register
Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins. Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank 0. In this mode, the pull-up/pull-downs will be disabled for I/O bank 0. Setting the bit 0 to logic 0 disables bus-hold feature. Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins. Setting the bit 1 to logic 1 enables selection of pull-up/pull-down using Register 6. Setting the bit 1 to logic 0 disables pull-up/pull-downs on the I/O bank 0 pins and contents of Register 6 will have no effect on the I/O.
Register 4 - Bus-hold/pull-up/pull-down enable 0 register (address 04h) bit description Legend: * default value. Bit 7 6 5 4 3 2 1 Symbol E0.7 E0.6 E0.5 E0.4 E0.3 E0.2 E0.1 Access R/W R/W R/W R/W R/W R/W R/W Value X X X X X X 0* allows the user to enable/disable pull-up/pull-downs on the I/O bank 0 pins 0 = disables pull-up/pull-downs on the I/O bank 0 pins and contents of Register 6 will have no effect on the I/O bank 0 (default value) 1 = enables selection of pull-up/pull-down using Register 6 0 E0.0 R/W 0* allows user to enable/disable the bus-hold feature for the I/O bank 0 pins 0 = disables bus-hold feature (default value) 1 = enables bus-hold feature
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Table 8.
Description not used
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
7.6.6 Register 5 - Bus-hold/pull-up/pull-down enable 1 register
Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins. Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank 1. In this mode, the pull-up/pull-downs will be disabled for I/O bank 1. Setting the bit 0 to logic 0 disables bus-hold feature. Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins. Setting the bit 1 to logic 1 enables selection of pull-up/pull-down using Register 7. Setting the bit 1 to logic 0 disables pull-up/pull-downs on the I/O bank 1 pins and contents of Register 7 will have no effect on the I/O.
Register 5 - Bus-hold/pull-up/pull-down enable 1 register (address 05h) bit description Legend: * default value. Bit 7 6 5 4 3 2 1 Symbol E1.7 E1.6 E1.5 E1.4 E1.3 E1.2 E1.1 Access R/W R/W R/W R/W R/W R/W R/W Value X X X X X X 0* allows the user to enable/disable pull-up/pull-downs on the I/O bank 1 pins 0 = disables pull-up/pull-downs on the I/O bank 1 pins and contents of Register 7 will have no effect on the I/O bank 0 (default value) 1 = enables selection of pull-up/pull-down using Register 7 0 E1.0 R/W 0* allows user to enable/disable the bus-hold feature for the I/O bank 1 pins 0 = disables bus-hold feature (default value) 1 = enables bus-hold feature Description not used Table 9.
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
7.6.7 Register 6 - Pull-up/pull-down select port 0 register
When bus-hold feature is not selected and bit 1 of Register 4 is set to logic 1, the I/O port 0 can be configured to have pull-up or pull-down by programming the pull-up/pull-down register. Setting a bit to logic 1 will select a 100 k pull-up resistor for that I/O pin. Setting a bit to logic 0 will select a 100 k pull-down resistor for that I/O pin. If the bus-hold feature is enabled, writing to this register will have no effect on pull-up/pull-down selection.
Table 10. Register 6 - Pull-up/pull-down select port 0 register (address 06h) bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 1* 1* 1* 1* 1* 1* 1* 1* Description configures I/O port 0 pin to have pull-up or pull-down when bus-hold feature not selected and bit 1 of Register 4 is logic 1 0 = selects a 100 k pull-down resistor for that I/O pin 1 = selects a 100 k pull-up resistor for that I/O pin (default value)
7.6.8 Register 7 - Pull-up/pull-down select port 1 register
When bus-hold feature is not selected and bit 1 of Register 5 is set to logic 1, the I/O port 1 can be configured to have pull-up or pull-down by programming the pull-up/pull-down register. Setting a bit to logic 1 will select a 100 k pull-up resistor for that I/O pin. Setting a bit to logic 0 will select a 100 k pull-down resistor for that I/O pin. If the bus-hold feature is enabled, writing to this register will have no effect on pull-up/pull-down selection.
Table 11. Register 7 - Pull-up/pull-down select port 1 register (address 07h) bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 1* 1* 1* 1* 1* 1* 1* 1* Description configures I/O port 1 pin to have pull-up or pull-down when bus-hold feature not selected and bit 1 of Register 5 is logic 1 0 = selects a 100 k pull-down resistor for that I/O pin 1 = selects a 100 k pull-up resistor for that I/O pin (default value)
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16-bit I2C-bus and SMBus, level translating, low voltage GPIO
7.6.9 Register 8 - Configuration port 0 register
This register configures the direction of the I/O pins. If a bit in this register is set (written with logic 1), the corresponding port 0 pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with logic 0), the corresponding port 0 pin is enabled as an output. At reset, the device's ports are inputs.
Table 12. Register 8 - Configuration port 0 register (address 08h) bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 1* 1* 1* 1* 1* 1* 1* 1* Description configures the direction of the I/O pins 0 = corresponding port pin enabled as an output 1 = corresponding port pin configured as input (default value)
7.6.10 Register 9 - Configuration port 1 register
This register configures the direction of the I/O pins. If a bit in this register is set (written with logic 1), the corresponding port 1 pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with logic 0), the corresponding port 1 pin is enabled as an output. At reset, the device's ports are inputs.
Table 13. Register 9 - Configuration port 1 register (address 09h) bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 1* 1* 1* 1* 1* 1* 1* 1* Description configures the direction of the I/O pins 0 = corresponding port pin enabled as an output 1 = corresponding port pin configured as input (default value)
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
7.6.11 Register 10 - Output port 0 register
This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Register 8. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 14. Register 10 - Output port 0 register (address 0Ah) bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 0* 0* 0* 0* 0* 0* 0* 0* Description reflects outgoing logic levels of pins defined as outputs by Register 8
7.6.12 Register 11 - Output port 1 register
This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Register 9. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 15. Register 11 - Output port 1 register (address 0Bh) bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 0* 0* 0* 0* 0* 0* 0* 0* Description reflects outgoing logic levels of pins defined as outputs by Register 9
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
7.6.13 Register 12 - Interrupt mask port 0 register
All the bits of Interrupt mask port 0 register are set to logic 1 upon power-on or software reset, thus disabling interrupts. Interrupts may be enabled by setting corresponding mask bits to logic 0.
Table 16. Register 12 - Interrupt mask port 0 register (address 0Ch) bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol M0.7 M0.6 M0.5 M0.4 M0.3 M0.2 M0.1 M0.0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 1* 1* 1* 1* 1* 1* 1* 1* Description enable or disable interrupts 0 = enable interrupt 1 = disable interrupt (default value)
7.6.14 Register 13 - Interrupt mask port 1 register
All the bits of Interrupt mask port 1 register are set to logic 1 upon power-on or software reset, thus disabling interrupts. Interrupts may be enabled by setting corresponding mask bits to logic 0.
Table 17. Register 13 - Interrupt mask port 1 register (address 0Dh) bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol M1.7 M1.6 M1.5 M1.4 M1.3 M1.2 M1.1 M1.0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value 1* 1* 1* 1* 1* 1* 1* 1* Description enable or disable interrupts 0 = enable interrupt 1 = disable interrupt (default value)
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
7.6.15 Register 14 - Interrupt status port 0 register
This register is read-only. It is used to identify the source of interrupt. Remark: If the interrupts are masked, this register will return all zeros.
Table 18. Register 14 - Interrupt status port 0 register (address 0Eh) bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol S0.7 S0.6 S0.5 S0.4 S0.3 S0.2 S0.1 S0.0 Access read only read only read only read only read only read only read only read only Value 0* 0* 0* 0* 0* 0* 0* 0* Description identifies source of interrupt
7.6.16 Register 15 - Interrupt status port 1 register
This register is read-only. It is used to identify the source of interrupt. Remark: If the interrupts are masked, this register will return all zeros.
Table 19. Register 15 - Interrupt status port 1 register (address 0Fh) bit description Legend: * default value. Bit 7 6 5 4 3 2 1 0 Symbol S1.7 S1.6 S1.5 S1.4 S1.3 S1.2 S1.1 S1.0 Access read only read only read only read only read only read only read only read only Value 0* 0* 0* 0* 0* 0* 0* 0* Description identifies source of interrupt
7.7 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9575 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9575 registers and state machine will initialize to their default states. The power-on reset typically completes the reset and enables the part by the time the power supply is above VPOR. However, when it is required to reset the part by lowering the power supply, it is necessary to lower it below 0.2 V.
7.8 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCA9575 registers and I2C-bus state machine will be held in their default state until the RESET input is once again HIGH.
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16-bit I2C-bus and SMBus, level translating, low voltage GPIO
7.9 Software reset
The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up state value through a specific formatted I2C-bus command. To be performed correctly, it implies that the I2C-bus is functional and that there is no device hanging the bus. The Software Reset sequence is defined as following: 1. A START command is sent by the I2C-bus master. 2. The reserved General Call I2C-bus address `0000 000' with the R/W bit set to 0 (write) is sent by the I2C-bus master. 3. The PCA9575 device(s) acknowledge(s) after seeing the General Call address `0000 0000' (00h) only. If the R/W bit is set to logic 1 (read), no acknowledge is returned to the I2C-bus master. 4. Once the General Call address has been sent and acknowledged, the master sends 1 byte. The value of the byte must be equal to 06h (1000 0011).The PCA9575 acknowledges this value only. If the byte is not equal to 06h, the PCA9575 does not acknowledge it. If more than 1 byte of data is sent, the PCA9575 does not acknowledge anymore. 5. Once the right byte has been sent and correctly acknowledged, the master sends a STOP command to end the Software Reset sequence: the PCA9575 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time. If the master sends a Repeated START instead, no reset is performed. The I2C-bus master must interpret a non-acknowledge from the PCA9575 (at any time) as a `Software Reset Abort'. The PCA9575 does not initiate a software reset.
7.10 Interrupt output (INT)
The open-drain active LOW interrupt is activated when one of the port pins changes state and the port pin is configured as an input and the interrupt on it is not masked. The interrupt is deactivated when the port pin input returns to its previous state or the Input Port register is read. It is highly recommended to program the MSK register, and the CFG registers during the initialization sequence after power-up, since any change to them during Normal mode operation may cause undesirable interrupt events to happen. Remark: Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. Only a Read of the Input Port register that contains the bit(s) image of the input(s) that generated the interrupt clears the interrupt condition.
7.11 Standby
The PCA9575 goes into standby when the I2C-bus is idle. Standby supply current is lower than 2.0 A (typical).
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
8. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 9).
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 9.
Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 10).
SDA
SCL S START condition P STOP condition
mba608
Fig 10. Definition of START and STOP conditions
8.2 System configuration
A device generating a message is a `transmitter'; a device receiving is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves' (see Figure 11).
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16-bit I2C-bus and SMBus, level translating, low voltage GPIO
SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER
SLAVE
002aaa966
Fig 11. System configuration
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition 1 2 8 clock pulse for acknowledgement
002aaa987
9
Fig 12. Acknowledgement on the I2C-bus
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
9. Bus transactions
Data is transmitted to the PCA9575 registers using `Write Byte' transfers (see Figure 13 and Figure 14). Data is read from the PCA9575 registers using `Read Byte' transfers (see Figure 15 and Figure 16).
SCL
1
2
3
4
5
6
7
8
9 command byte data to port 1 0 A acknowledge from slave DATA 1 A STOP condition P
slave address(1) SDA S 0 1 0 0 0 0 0 0 R/W A 0 0
0
0
1
0
START condition write to port
acknowledge from slave
acknowledge from slave
tv(Q) data out from port DATA 1 VALID
002aad569
(1) Slave address shown in this example is for the 24-pin version.
Fig 13. Write to Output port register
SCL
1
2
3
4
5
6
7
8
9 command byte data to register X X A acknowledge from slave DATA A STOP condition P
slave address(1) SDA S 0 1 0 0 0 0 0 0 R/W A 0 0
0
0
X
X
START condition data to register
acknowledge from slave
acknowledge from slave
002aad570
(1) Slave address shown in this example is for the 24-pin version.
Fig 14. Write to Polarity inversion, Bus-hold enable, Pull-up/pull-down select, Configuration, Interrupt mask and Interrupt status registers
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
slave address(1) SDA S 0 1 0 0 0 0 0 0 R/W acknowledge from slave slave address(1) (cont.) S 0 1 0 0 0 0 0 1 R/W acknowledge from slave A A command byte A (cont.)
START condition
acknowledge from slave data from register DATA (first byte) A data from register DATA (last byte) NA P STOP condition
(repeated) START condition
acknowledge from master
no acknowledge from master
at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter
002aad571
(1) Slave address shown in this example is for the 24-pin version.
Fig 15. Read from register
DATA 2 data into port th(D) INT tv(INT) SCL 1 2 3 4 5 6 7 8 9 data from port 0 1 R/W A acknowledge from slave DATA 1 A acknowledge from master data from port DATA 4 no acknowledge from master trst(INT) DATA 3 tsu(D) DATA 4
slave address(1) SDA S 0 1 0 0 0 0
1
P STOP condition
START condition read from port
002aad572
This figure assumes the command byte has previously been programmed with 00h. Transfer of data can be stopped at any moment by a STOP condition. (1) Slave address shown in this example is for the 24-pin version.
Fig 16. Read Input port register
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
10. Application design-in information
VDD(IO)1 = 3.6 V VDD(IO)0 = 3.6 V SUBSYSTEM 4 (e.g., RF module) VDD VDD(IO)1 VDD(IO)0 CTRL SUBSYSTEM 1 (e.g., temp. sensor) INT RESET SUBSYSTEM 2 (e.g., counter) A enable 10 DIGIT NUMERIC KEYPAD controlled switch (e.g., CBT device) B ALARM SUBSYSTEM 3 (e.g., alarm system)
VDD = 1.1 V to 3.6 V
1.6 k 1.6 k 1.1 k 2 k
VDD MASTER CONTROLLER SCL SDA INT RESET VSS
PCA9575
SCL SDA INT RESET P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7 P1_0 P1_1 P1_2 A0 A1 A2 A3 VSS P1_3 P1_4 P1_5 P1_6 P1_7
VDD(IO)0
002aad573
Address pin connections shown are for the 28-pin version. Device address configured as 0100 101Xb for this example. P0_0, P0_2, P0_3 configured as outputs; P0_1, P0_4 to P0_7 and P1_0 to P1_7 configured as inputs.
Fig 17. Typical application
11. Limiting values
Table 20. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VDD(IO)0 VDD(IO)1 II/O II IDD ISS Ptot Tstg Tamb Parameter supply voltage input/output supply voltage 0 input/output supply voltage 1 input/output current input current supply current ground supply current total power dissipation storage temperature ambient temperature Conditions Min -0.5 VSS - 0.5 VSS - 0.5 -65 -40 Max +4.0 VDD + 0.5 VDD + 0.5 5 20 90 90 75 +150 +85 Unit V V V mA mA mA mA mW C C
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16-bit I2C-bus and SMBus, level translating, low voltage GPIO
12. Static characteristics
Table 21. Static characteristics VDD = 1.1 V to 3.6 V; VDD(IO)0 = 1.1 V to 3.6 V; VDD(IO)1 = 1.1 V to 3.6 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VDD VDD(IO)0 VDD(IO)1 IDD IstbL IstbH supply voltage input/output supply voltage 0 input/output supply voltage 1 supply current LOW-level standby current HIGH-level standby current operating mode; VDD = 3.6 V; no load; fSCL = 100 kHz; I/O = inputs Standby mode; VDD = 3.6 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs Standby mode; VDD = 3.6 V; no load; VI = VDD(IO)0 = VDD(IO)1; fSCL = 0 kHz; I/O = inputs no load; VI = VDD or VSS (rising VDD) 1.1 1.1 1.1 135 0.25 0.25 3.6 VDD + 0.5 VDD + 0.5 200 2 2 V V V A A A Parameter Conditions Min Typ Max Unit
VPOR VIL VIH IOL IL Ci I/Os VIL VIH IOL
power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current leakage current input capacitance LOW-level input voltage HIGH-level input voltage LOW-level output current
-0.5 0.7VDD
0.7 6 3 100 3.7 3.7
1.0 +0.3VDD 3.6 +1 10 +0.3VDD 3.6 150 1 -1 5 5
V V V mA mA A pF V V mA mA V k A A A A pF pF
Input SCL; input/output SDA
VOL = 0.2 V; VDD = 1.1 V VOL = 0.4 V; VDD = 2.3 V VI = VDD or VSS VI = VSS
1 3 -1 -0.5 0.3VDD
VOL = 0.2 V; VDD(IO)0 = 1.1 V; VDD(IO)1 = 1.1 V VOL = 0.5 V; VDD(IO)0 = 3.6 V; VDD(IO)1 = 3.6 V
1 2 0.8 50
VOH Rpu(int) ILIH IH
HIGH-level output voltage internal pull-up resistance HIGH-level input leakage current holding current
IOH = -1 mA; VDD(IO)0 = 1.1 V; VDD(IO)1 = 1.1 V VDD(IO)0 = 3.6 V; VDD(IO)1 = 3.6 V; VI = VDD(IO)0; VI = VDD(IO)1 VI = 0.3 V; VDD(IO)0 = 1.1 V; VDD(IO)1 = 1.1 V; VDD = 3.6 V VI = 0.8 V; VDD(IO)0 = 1.1 V; VDD(IO)1 = 1.1 V; VDD = 3.6 V
10 -10 -
ILIL Ci Co
LOW-level input leakage current input capacitance output capacitance
VDD(IO)0 = 3.6 V; VDD(IO)1 = 3.6 V; VI = VSS
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
Table 21. Static characteristics ...continued VDD = 1.1 V to 3.6 V; VDD(IO)0 = 1.1 V to 3.6 V; VDD(IO)1 = 1.1 V to 3.6 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol IOL VIL VIH ILI Ci Parameter LOW-level output current LOW-level input voltage HIGH-level input voltage input leakage current input capacitance Conditions VOL = 0.4 V; VDD = 1.1 V Min 3 VDD - 0.2 -1 Typ 2 Max +0.2 +1 4 Unit mA V V A pF Interrupt INT Select inputs (reset and address)
3.0 VOH (V) 2.0
002aae767
4.0 VOH (V) 3.0
002aae768
2.0 1.0 1.0
0 -40
-20
0
20
40
60
100 Tamb (C) 80
0 -40
-20
0
20
40
60
100 80 Tamb (C)
Fig 18. VOH at VDD = 3.3 V, VDD(IO)n = 1.2 V, IOH = -1 mA
Fig 19. VOH at VDD = 3.3 V, VDD(IO)n = 3.3 V, IOH = -1 mA
40 IOL (mA) 30 Tamb = -40 C +25 C +85 C
002aaf069
60 IOL (mA) 40 Tamb = -40 C +25 C +85 C
002aaf070
20
20 10
0 0 200 400 600 800 VOL(typ) (V)
0 0 200 400 600 800 VOL(typ) (V)
a. VDD(IO)0 or VDD(IO)1 = 1.8 V Fig 20. IOL versus VOL
b. VDD(IO)0 or VDD(IO)1 = 2.6 V
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
24 IOH (mA) 16 Tamb = -40 C +25 C +85 C
002aaf071
40 IOL (mA) 30 Tamb = -40 C +25 C +85 C
002aaf072
20
8 10
0 0 0.2 0.4 0.6 0.8 VDD - VOH (V)
0 0 0.2 0.4 0.6 0.8 VDD - VOH (V)
a. VDD(IO)0 or VDD(IO)1 = 1.8 V Fig 21. IOH versus VOH
b. VDD(IO)0 or VDD(IO)1 = 2.6 V
13. Dynamic characteristics
Table 22. Dynamic characteristics VDD = 1.1 V to 3.6 V; VDD(IO)0 = 1.1 V to 3.6 V; VDD(IO)1 = 1.1 V to 3.6 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Standard-mode I2C-bus Min fSCL tBUF tHD;STA tSU;STA tSU;STO tVD;ACK tHD;DAT tVD;DAT tSU;DAT tLOW tHIGH tf tr tSP SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data valid acknowledge time data hold time data valid time data set-up time LOW period of the SCL clock HIGH period of the SCL clock fall time of both SDA and SCL signals rise time of both SDA and SCL signals pulse width of spikes that must be suppressed by the input filter
[2] [1]
Fast-mode I2C-bus Unit Min 0 1.3 0.6 0.6 0.6 0.1 0 50 100 1.3 0.6 20 + 0.1Cb[3] 20 + 0.1Cb[3] Max 400 0.9 300 300 50 kHz s s s s s ns ns ns s s ns ns ns
Max 100 3.45 300 1000 50
0 4.7 4.0 4.7 4.0 0.3 0 300 250 4.7 4.0 -
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16-bit I2C-bus and SMBus, level translating, low voltage GPIO
Table 22. Dynamic characteristics ...continued VDD = 1.1 V to 3.6 V; VDD(IO)0 = 1.1 V to 3.6 V; VDD(IO)1 = 1.1 V to 3.6 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Standard-mode I2C-bus Min Port timing tv(Q) data output valid time VDD(IO)0, VDD(IO)1 = VDD = 1.1 V VDD(IO)0, VDD(IO)1 = VDD = 2.3 V to 3.6 V tsu(D) th(D) tv(INT) trst(INT) Reset tw(rst) reset pulse width VDD(IO)0, VDD(IO)1 = VDD = 1.1 V VDD(IO)0, VDD(IO)1 = VDD = 2.3 V to 3.6 V trec(rst) trst(SDA) trst(GPIO)
[1] [2] [3]
Fast-mode I2C-bus Unit Min 150 1 8 4 0 Max 350 300 4 4 400 400 ns ns ns s s s ns ns ns ns ns
Max 350 300 4 4 400 400
150 1 8 4 0
data input set-up time data input hold time valid time on pin INT reset time on pin INT
Interrupt timing
reset recovery time SDA reset time GPIO reset time Figure 23 Figure 23
-
tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. Cb = total capacitance of one bus line in pF.
SDA tBUF tLOW SCL tr tf tHD;STA tSP
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
002aaa986
Fig 22. Definition of timing
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PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
START SCL
ACK or read cycle
SDA 30 %
30 % trst(SDA)
RESET
50 % trec(rst)
50 % tw(rst)
50 % trst(GPIO) 50 % output off
002aad574
P0_0 to P0_7 P1_0 to P1_7
Fig 23. Reset timing
14. Test information
2VDD open VSS
VDD PULSE GENERATOR VI DUT
RT
VO
RL 500
CL 50 pF
500 (1)
002aad582
RL = load resistance. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generators. (1) For SDA, no 500 pull-down.
Fig 24. Test circuitry for switching times
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16-bit I2C-bus and SMBus, level translating, low voltage GPIO
15. Package outline
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
D
E
A
X
c y HE vMA
Z
24
13
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
12
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8o 0o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 25. Package outline SOT355-1 (TSSOP24)
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NXP Semiconductors
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm
SOT361-1
D
E
A
X
c y HE vMA
Z
28
15
Q A2 pin 1 index A1 (A 3) A
Lp L detail X
1
e bp
14
wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 9.8 9.6 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.5 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT361-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 26. Package outline SOT361-1 (TSSOP28)
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Product data sheet
Rev. 03 -- 9 November 2009
31 of 38
NXP Semiconductors
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.75 mm
SOT994-1
D
B
A
terminal 1 index area E A A1 c
detail X
e1 1/2 e e
7
b
12
v w
M M
CAB C
C y1 C y
L
6 13
e
Eh 1/2 e
1
e2
18
terminal 1 index area
24
19
Dh
X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 0.8 A1 0.05 0.00 b 0.30 0.18 c 0.2 D(1) 4.1 3.9 Dh 2.25 1.95 E (1) 4.1 3.9 Eh 2.25 1.95 e 0.5 e1 2.5 e2 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT994-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 07-02-07 07-03-03
Fig 27. Package outline SOT994-1 (HWQFN24)
PCA9575_3 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 9 November 2009
32 of 38
NXP Semiconductors
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
PCA9575_3 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 9 November 2009
33 of 38
NXP Semiconductors
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 17.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 28) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 23 and 24
Table 23. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 24. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 28.
PCA9575_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 9 November 2009
34 of 38
NXP Semiconductors
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 28. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
18. Abbreviations
Table 25. Acronym CBT CDM CMOS DUT ESD GPIO HBM I/O I2C-bus IC LED LP MM PLC POR RAID RF SMBus Abbreviations Description Cross Bar Technology Charged Device Model Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge General Purpose Input/Output Human Body Model Input/Output Inter-Integrated Circuit bus Integrated Circuit Light Emitting Diode Low Pass Machine Model Programmable Logic Controller Power-On Reset Redundant Array of Independent Discs Radio Frequency System Management Bus
PCA9575_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 9 November 2009
35 of 38
NXP Semiconductors
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
19. Revision history
Table 26. Revision history Release date 20091109 Data sheet status Product data sheet Change notice Supersedes PCA9575_2 Document ID PCA9575_3 Modifications: PCA9575_2 PCA9575_1
* *
Added Figure 20 "IOL versus VOL". Added Figure 21 "IOH versus VOH". Product data sheet Product data sheet PCA9575_1 -
20090727 20081002
PCA9575_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 9 November 2009
36 of 38
NXP Semiconductors
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
20. Legal information
20.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
20.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9575_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 9 November 2009
37 of 38
NXP Semiconductors
PCA9575
16-bit I2C-bus and SMBus, level translating, low voltage GPIO
22. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.6.7 7.6.8 7.6.9 7.6.10 7.6.11 7.6.12 7.6.13 7.6.14 7.6.15 7.6.16 7.7 7.8 7.9 7.10 7.11 8 8.1 8.1.1 8.2 8.3 9 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . . 8 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 8 Command register . . . . . . . . . . . . . . . . . . . . . . 9 Register definitions . . . . . . . . . . . . . . . . . . . . . . 9 Writing to port registers . . . . . . . . . . . . . . . . . 10 Reading the port registers . . . . . . . . . . . . . . . 10 Register 0 - Input port 0 register. . . . . . . . . . . 10 Register 1 - Input port 1 register. . . . . . . . . . . 11 Register 2 - Polarity inversion port 0 register . 11 Register 3 - Polarity inversion port 1 register . 12 Register 4 - Bus-hold/pull-up/pull-down enable 0 register . . . . . . . . . . . . . . . . . . . . . . . 12 Register 5 - Bus-hold/pull-up/pull-down enable 1 register . . . . . . . . . . . . . . . . . . . . . . . 13 Register 6 - Pull-up/pull-down select port 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Register 7 - Pull-up/pull-down select port 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Register 8 - Configuration port 0 register . . . . 15 Register 9 - Configuration port 1 register . . . . 15 Register 10 - Output port 0 register . . . . . . . . 16 Register 11 - Output port 1 register . . . . . . . . 16 Register 12 - Interrupt mask port 0 register . . 17 Register 13 - Interrupt mask port 1 register . . 17 Register 14 - Interrupt status port 0 register. . 18 Register 15 - Interrupt status port 1 register. . 18 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 18 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 19 Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 19 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Characteristics of the I2C-bus. . . . . . . . . . . . . 20 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 START and STOP conditions . . . . . . . . . . . . . 20 System configuration . . . . . . . . . . . . . . . . . . . 20 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 21 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 22 10 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 20 20.1 20.2 20.3 20.4 21 22 Application design-in information . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Test information. . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 25 27 29 30 33 33 33 33 33 34 35 36 37 37 37 37 37 37 38
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 November 2009 Document identifier: PCA9575_3

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